Division by preselected divisor



Sept. 26, '1967 Filed Sept. 28, 1965 2 Shets-Sheet 1 FIG.1 4

000mm q q 9m REGISTER (X+n) x+2) x+n OUOTIENT LOGIC (ASIN d d d DIVIDEND(x+n) (x+2) (XH) (x) STORE INVENTOR.

LOUiS M. HORNUNG ATTORNEY.

United States Patent 3,344,261 DIVISION BY PRESELECTED DIVISOR Louis M.Hornung, Lexington, Ky., assignor to International Business MachinesCorporation, Armonk, N.Y., a corporation of New York Filed Sept. 28,1965, Ser. No. 490,895 15 Claims. (Cl. 235-160) This invention relatesto the machine division of one number by another. The invention isparticularly useful for implementation of a division step in a radixconversion operation, but division for other purposes is also within thescope of this invention.

Division is a significant problem in the data processing art. Means todivide are known, of course, but the known means require a large, andconsequently time consuming and structurally complicated, number ofsteps. For example, one common method of machine division is the same ora modification of the pencil and paper division used almost universallyby individuals in this country. Such a division requires at least onecomplete subtraction of the divisor or a multiple of the divisor fromsome number for each significant ordinal of the quotient.

No division method is known in the prior art which reaches a quotient inanumber of memory access cycles strictly limited to the number ofordinals in the quotient. It 'isian object .of this invention to providesuch a potentially high speed divider. Indeed, division can beaccomplished in accordance with this invention in an interval of timeapproaching that required for the addition of two binary numbers by thefastest electronic mechanisms known today. It is a related object ofthis invention to provide an electronic data processing machine dividerwhich is faster for the purpose used than any practical, known divider.It is a further related object of this invention to provide a dividerwhich can be used to make possible high speed machine radix conversion.

The machine divider in accordance with this invention constitutesmachine elements and parts permanently structured to divide by apreselected divisor. Dividers of this nature are known which arereasonably-limited in extra structure required. This invention, however,also requires only a small amount of structure and structuralcomplications, and the invention further provides the high speedcapabilities discussed above. It is therefore a further object of thisinvention to provide a high speed divider as specified in which thestructural requirements are not inordinate. The invention allows the useof structures which are both practical and economic.

In accordance with this invention means are provided to obtain aresponse condition based upon the status of certain high orders of thequotient and certain high orders of the dividend. No prior art is knownwhich uses these two factors in any similar way. The value of a lowerordinal of the quotient is generated in accordance with the responsecondition. This new quotient ordinal is stored or preserved in some wayfor use in a second comparison of the same kind as the first comparisonto generate another lower quotient ordinal. This repetitive sequence canbe continued until the division is complete.

3,344,261 Patented Sept. 26, 1967 The divider in accordance with thisinvention is particularly useful with structures permanently built intoa machine for division by a preselected factor. The inventionistherefore particularly valuable for radix conversion such as, theconversion of a natural bianry number to a number in radix ten by theknown algorism of repetitively dividing by ten. (Division by ten canbepartitioned into a division by two and a division by five, the formerbeing merely a matter of a column shift, as is well konwn.) Division bya factor other than ten can be used to achieve a conversion to adifferent radix. Division for other ultimate purposes is also, ofcourse, apart of the subject matterof this invention.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of preferred embodiments of the invention, as illustrated inthe accompany drawings.

FIG. 1 illustrates a preferred system to divide a natural binary numberin a machine by a preselected value such as five.

FIG. 2 illustrates the best known combination of logical elements usedto determine one ordinal of the new quotient for division by five.

FIG. 3 illustrates a preferred version.

FIG. 4 illustrates the preferred decode logic for. use with FIG. 3. q

THE PREFERRED OPERATION In practicing this invention in this preferredsystem, in which a natural binary number is divided by five, it isrequired to have means capable of simultaneously supplying-three ordinalvalues of the quotient and four ordinal values of the divisor. Most dataprocessing equipments store these numbers, but do not provide forsimultaneous access to these specific bits. Provision of such accessingmeans, however, is well within the state of the art.

If any specific, unknown quotient ordinal is arbitrarily denominated asq then the quotient'values which must system for radix con- 7 besupplied in this preferred embodiment are: q(X+1) i.e.,

one ordinal higher q(x+2) i.e., two ordinals higher, and q(X+3) i.e.,three ordinals higher. Using the same arbitrary definitions, thedenominators which must be supplied are d a d and d Since .both of thesenumbers are in the natural binary notation, each ordinal may have eithera significance of one or a significa'nceof zero. The following KarnaughMap completely describes the results which should be generated inaccordance with this preferred embodiment for all simultaneousexaminations of the three quotient ordinals and the four dividendordinals. The logic diagram illustrated in FIG. 2 will be recognized,upon careful study, as a good structural implementation of the KarnaughMap. Although better implementations of the Karnaugh Map may bepossible, FIG. 2 is believed at this time to be the best known. TheKarnaugh Map, of course, is' simply a table which is well suited tolocate the result which follows from seven variables. For thoseunfamiliar with such a table, an example will be detailed here.

uest ean ear Ones and zeros values of the terms dictate whether thequantities inside or outside the brackets for the terms are to beconsidered on the map.

In using the map, the q =1 term means that the part of the map withinthe q brackets is isolated. Thus, the bottom half of the map isisolated.

The q term further isolates the map at those parts Without the (1brackets. Thus, the first and second rows frow the bottom are isolated.

The q =1 term isolates only those rows within the q(x+1) brackets on themap. Thus, reference to the three q terms has isolated one, single row;and that row is the second from the bottom.

The d terms are further operative to isolate a single box in theisolated row.

Thus, the d =0 term isolates the left side of the map.

The d =1 term further isolates the four boxes of the map on the leftfrom the center of the map.

The d =O term further isolates those boxes which are without the dbrackets, in this case the two boxes immediately to the left of thecenter of the map.

The d g-=1 term finally isolates that single box which is defined by allthe d and q terms by the isolations as above described. Since d =1, thebox within the d brackets is isolated. This is the seventh box from theleft in the second row from the bottom (the row, of course, was isolatedby the q terms as above described).

One box on the map has been thus defined. The result is described by thecontents of this box, zero in this case. (Boxes containing an X willnever be isolated in a true division. The X is therefore just a fillerfor these boxes in the map.)

It should be understood, of course, that the Karnaugh Map is of primaryvalue only for use in machine design and'for use to explain thisinvention. In an actual machine the map is implemented by Boolean logicof the kind shown in FIG. 2. Electronic circuits of various kinds areknown which can implement the logic of FIG. 2. Many conventionalcircuits implementing FIG. 2 are capable of resolving the quotientordinal in a fraction of a microsecond, the only delay being the timerequired for the circuit to settle to the conditions forced upon thecircuit by the simultaneous inputs to the circuit.

In carrying through a complete division, it is necessary, of course, torepeat the quotient ordinal determination for the several quotientsgenerated, and to be able to access the lower ordinals of the dividendas needed.

ILLUSTRATIVE CYCLE Purely as an example, the division by five of thenatural binary number six will be detailed. The natural binary numbersix is stored in a machine as follows, assuming for purposes ofillustration that the 8 ordinal is the high est ordinal stored in themachine.

Ordinal Value: 8 4 2 1 Significance: 0 1 1 0 The number is examined highorder first, and, of course, the significance of each quotient ordinalis generated high order first. Since the highest ordinal in thissimplified example is 8, the significance of the 8 ordinal of thedividend is first accessed. All registers containing input values to thedivider should be cleared before the Operation begins.

Thus, referring to FIG. 1, the partial quotient store 1 and the partialdividend store 3 each contain significances of zero, including theordinal, which in this case is the 8 ordinal, which has a significanceof zero. Reference to the map isolates the upper left hand box, whichcontains a zero; the same result is reached by the circuits of FIG. 2,as illustrated by the quotient logic 5 of FIG. 1. Thus, the significanceof the 8 ordinal of the quotient is defined by the structures as zero.

The new quotient ordinal significance, zero in this case, is thenshifted into the partial quotient store 1. The higher ordinals, zero atthis time, are shifted into their respective next higher order positionsof the quotient register 7 for more permanent storage and use in themachine. Simultaneously, the dividend is shifted into the partialdividend store 3 and the high orders in the store 3 are destroyed orpossibly routed back into some machine storage for future use as needed.Since the original dividend value was six, it is necessarily impliedthat all ordinals below the binary point have a significance of zero.Therefore, simultaneously with the shift in the dividend a zero isinserted into the lowest stage of dividend store 9.

Immediately after the shift, which may be conducted in a fewmicroseconds when solid state elements and toroidal magnetic memorycores are used, a new ordinal of the quotient may be computed. Toaccomplish this the quotient logic 5 is pulsed with the values stored inpartial quotient store 1 and partial dividend store 3. In this case ofdivision of six every value observed is zero except doe which has asignificance of one. From FIG. 2 it will be clear that a value of zerowill be generated by quotient logic 5. This can be verified by the map,in which the second box from the left in the top row is isolated. Thus,the significance of the quotient ordinal having the value 4 isdetermined to be zero. The shifts as above described are conducted onceagain.

With the shift completed the values of q q q(x+1) stored in partialquotient store 1 are once again all zero. The values in partial divisorstore 3 are d d =0; d =1; d =1. Quotient logic is again made operative.Once again a zero is generated. With reference to the map, this zero isfound in the top row, the third box from the left. Thus, the 2 ordinalof the quotient is computed as having a significance of zero.

Once again the values are shifted. After the shift, the values are asfollows: q =0; q =0; q =0; d =0; d =l; =1; d =0. The quotient logic 5 ispulsed, and a one is produced. This is verified by the map, the fifthbox from the left of the top row is the one isolated. In this manner theone valued ordinal of the quotient is found to have a significance ofone.

The shift is again conducted. After the shift, the values are asfollows: q =0; q =0; q =1; d =1; d =1; d =O; d =0. The quotient logic 5is pulsed, and a zero is produced. This is verified by the map, theninth box from the left in the second row from the top being isolated.The value of the ordinal of the quotient is thus found to have asignificance of zero.

The shift is again conducted. After the shift, the values are asfollows: q =0; q =1; q =0; d =1; d =0; d =0; d =0. The quotient logic 5is pulsed, and a zero is produced. This is verified by the map, thesixteenth box from the left of the fourth row from the top beingisolated. The value of the A ordinal of the quotient is thus found tohave a significance of zero.

' The shift is again conducted After the shift, the values I are asfollows: q =l; q =0; q =0; d =O; a' =0; d ='0; d =0. The quotient logic5 is pulsed, and a one is produced. This is verified by the map, thefirst box from the left in the bottom row being the one isolated. Thevalue of the /8 ordinal of the quotient is thus found to have asignificance of one.

The shift is again conducted. After the shift, the values are asfollows: q =0; q =0; q =1; d =0; d =0; d =0; d =0. The quotient logic 5is pulsed, and a one is produced. This is verified by the map, the firstbox from the left in the second row from the top being the one isolated.The value of the A ordinal of the quotient is thus found to have asignificance of one.

The above can be continued further and, theoretically, indefinately toproduce the value below the binary point in a fractional expansion. Itshould be clear that the correct significance of each ordinal of thequotient is generated on one pass through the dividend high order firstin a system which is basically capable of great speed. The structuresinvolved are not complicated or expensive, being, as a matter of fact,comparable to that required in an adding-subtracting accumulator. Itshould betclear that the implementation need not be in a seriallyshifted memory as discussed for purposes of example in the abovedivision of six by five. It is an important capability of this inventionthat it can be implemented using cascaded quotient logic structures,each as shown in FIG. 2 or modified as will be made clear below fordivision by some other divisor. The higher order quotient logic circuitswill be connected as inputs to the lower order quotient logic circuitsto the limited extent required by this invention. The entire dividendwill be accessed simultaneously into the cascaded structures, also tothe limited extent required by this invention. The entire quotient willthereby be generated at great speed in a single machine step in aparallel machine.

The above structures and steps are capable of explanation and expansionon theoretical grounds, and I have made these theoreticaldeterminations.

THEORYDIVISION BY FIVE It was noted that the following is invariablytrue when the quotient is /5 of the divisor. [In the equations the 4values are the ordinals of the quotient, the d values are the ordinalsof the dividend, x is a whole number used as subscript to mathematicallydefine the continuous sequence of ordinals under consideration (thus, innatural binary the 8 ordinal could arbitrarily be defined as the xordinal, then the 16 ordinal is the x+1 ordinal), and the C values arecarries from the addition of lesser ordinals] ows) 2 +d (xi-2) 2 (x+1)(X) 2X Equation A is seen to be true by the following explanation.Representing the dividend by D and the quotient by Q, the division byfive responds to the equality As is well understood, a shift by twoordinal positions of any number described in the natural binary schemeof notation constitutes an automatic multiplication of that number byfour. The ordinals of the quotient arranged in additive columns inEquation A are displaced by two ordinal positions (x describes theordinal sequence in Equation A). Thus, Equation A is verified since itis an implementation of the equation D=Q+4Q, in which certain portionsare selected out of the body of the entire natural binary numberdescriptions for the values of D, Q, and 4Q, and the two ends of thequotients portions used in Equation A additionally contain the carryvalues possible in any addition. C describes the total value of carriesfrom the low orders and therefore completely describes the influence oflow orders of Q and 4Q on the portions of those numbers selected forEquation A. The C(X+3) value completely describes the transfer of valueto higher ordinals generated by the portions selected for Equation A.

With the above as one formula, two other equations were derived fromtheory of numbers.

C was defined by the properties of addition, which inherently imply thefollowing, which is an exhaustive logical analysis'of all possibleadditions in an'ordinal containing C(x+3) in the manner shown inEquation A. Assuming q q(x+1) and d x+s are known, the followingequations are written in standard Boolean terms where means AND, I-means OR, and overline means NOT: Thus, in standard Boolean fashion, C=1 when Equation B below is satisfied, Otherwise the result is C whichimpliesC ;=0.

l d+s qd+nq +ol l o+s q o+nqt +ml With Equation B thus established, itis recognized that Equation A above can berewritten as a specificequality if the 2 term is removed by the expedient of dividing everyterm of Equation A by 2 Since Equation A is an algebraic equality,division of all terms by 2 is, of course, proper. Therefore, thefollowing is derived from Equation A.

Equation C A can be no greater than one. Therefore, 2q 2,

q 1 and C 51. Consequently,

q(x-1)+q(x+2)+ (x) must'be equal to or less than four in value.

Separately and additionally, q in Equation C is recognized as beingeither one or zero. Sorne different or intermediate value is notpossible, assuming the quotient is being generated in natural binarynotation and that the division responds, as it clearly must, to theusual limitations and theory of division. In consequence, the

quantity inside the brackets in Equation C, since it is preceded by /s,invariably must be divisible by five.

With even divisibility by five established and with 2q +q C known to beno greater than four,

it is then established and recognized by inspection of 5 Equation C thatEquation C permits of solution dictated only by the d values of d andgreater and by the q values of q(x+1) and greater, assuming C(x+3) isknown. The importance of Equation B then becomes evident since EquationB describes C(x+3) in terms of only the high virtually any form needed.Thus, in the case of a division by 9, Equation D would read For adivision by 10, Equation D would read 2D 8D ra ur Division of both sidesof Equation D by D and multiplication of both sides of Equation D by Vmakes it clear that the v terms (v v are related to V as follows: V=v 2v 2 +v 2 +v 2 +v 2. Equation D, however, is best considered at this timewith reference to the theoretical proof of this invention. It should beevident from inspection of Equation D that Equation D is a generalexpression of a form representing any Whole number value of V. Anexample in addition to those above establishing this would be for V=1l,in which instance Equation D reads D 2D 8D D 11 11 11 Therefore, in themanner of Equation A, with which the division by 5 was proved, a generaladditive equation can be written in which certain portions are selectedout of the body of the entire natural binary number descriptions for thequotients. That equation is verified by the completely general EquationD. The completely general additive equation is the following Equation E:

order values. With this firm theoretical basis, the Karnaugh Map fordivision by 5 above shown was constructed by systematically insertingeach possible combination into Equation B and Equation C so as to solvefor g Each value of q thus obtained constituted the value to be insertedin the box defined by all of the variables on the map.

VARIOUS DIVISORS This invention is useful to accomplish division withwhere: D is the dividend, V is the divisor, v v v v are eachindividually either one or zero as required by the value of V in orderto render Equation D an algebraic equality, and s is the highestsignificant ordinal of the expansion in Equation D.

The term D/ V is, of course, also the quotient, Q. Thus, Equation D mayalso be written as:

The direct relationship to the equality D=Q+4Q, used in the proof fordivision by 5, becomes more evident.

Equation E is completely general. In a particular case each individual vvalue may be one or zero. For division by 5, Equation A is a specificimplementation of Equation E. For a division by 7, Equation E wouldappear as follows:

As in the manner of Equation B in the proof for 'division by 5, ageneral equation for the highest order carry in Equation E, C 2 isrequired. That general. 5 equation can be obtained by consideration ofonly the addition columns including the column in which c(x+s+l) appearsin an addition similar to that described by Equation E and also, asdiscussed below, a finite number of higher order addition columns. Thisapproach is based upon the realization that all q and d values in thosehigh ordinal columns will be known during the machine division.

The basic approach is to realize that if the d value, i.e. d(x+s+l) isone, then an odd number of 1 values must exist for all of the q valuesin the additive column if the carry has a significance of zero, and,conversely, an even number exlsts if carry significance is one.Similarly, if the d value is zero, then an even number of 1 values must0 exist for all of the q values in the additive column if the carry hasa significance of zero, and, conversely, an odd number exists for acarry of one. In the general case here in under consideration a largenumber of possible numbers added increases greatl the number ofrelationships of factors which combine to describe C X+s+1 in terms ofEquation D is capable of specific implementation in the known high ordervalues. A significant complication is that the significance of a carryin an addition of natural binary numbers added in the manner of EquationE may be between the values of zero and one less than the total of vterms which have a significance of one. For example, one column in themiddle of the addition of four binary numbers may produce a carry havingany whole number value of 0, 1, 2, or 3.

Thus, Equation B was simplified because the carry could have asignificance of Only 1 or zero. In the more general case the carry Cx+s+n should be considered to have possible significance of 1 not onlyin the next higher column of Equation E, but also in a number of highercolumns, limited, however, by the fact that the carry can not be of avalue greater than the v m -1, where v is the sum of v terms having asignificance of one.

Stated mathematically, the high order columns may be written as follows:

Since COM) is known to be finite, it can be written in the naturalbinary form,

(x+s+1) t t- 1 "H Substitution of this natural binary form for Cam) inEquation F yields the following Equation G: The value The significancesof the b values in Equation G are the only values assumed to be unknown,since the other values are high order. Furthermore, the b values inEquation G are either one or zero, since the b values represent theordinal significance of a natural binary expression. Equation G istherefore capable of straightforward manipulation with the AND, OR logicof Boolean algebra. The following Equation H results, which, althoughmore complicated, is entirely comparable to specific Equation B.

Equation H b =1 when any combination of one significances of 0q(x+s+1):1q(x+s): 2q(x+s-1)1 s 1q X+2) and v q is even and d(x+5+1) is one; orwhen any combination of the same v values is odd and d(x+s+1) is zero.Otherwise, [Jo-=0.

b n =1 when any combination of one significances of 0 (x+s+t): 1q x+s+t1 2q(x+s+t-2): s-1 (x+t+1) and v qi and the one significance of anycarries from all the lower stages beginning with the stage containing his even and d(x+s+t) is one; or when any combination of the same vvalues and carry value is odd and d(x+s+1) is zero. Otherwise b ==0.

b =1 when any combination of one significances of 0 (x+s+t+1): 1q x+s+t1 2q(x+s+t1) s-1q(x+t+2): and v q and the one significance of anycarries from all the lower stages beginning with the stage containing his even and d(x+s+t+1) is one; or when any combination of the same vvalues is odd and d x+s+t+1 is zero. Otherwise, b =0.

The above type of logic is also true, of course, for b valuesintermediate between h and b With Equation H established, it thenbecomes. desirable to rewrite Equation E as a specific equality in the10 manner that Equation A was rewritten as Equation C is the proof fordivision by 5. By dividing both sides of the equality expressed byEquation E by 2 and by straightforward algebraic manipulation ofEquation E, the following Equation I is obtained:

Quantities in Equation I with ordinal values as low as q and lower forthe purposes of a division by machine should be viewed as unknown andnot directly attainable. Also, C for the purposes of division should beviewed as unknown and not directly attainable. The quantities weregrouped at the end of the brackets in Equation I. They may be defined asa quantity u. Thus, Equation J follows:

Equation J As in the proof for division by 5, it is the maximum negativevalue of u which is of interest, the minimum value, of course, clearlybeing zero. Therefore, "all of the q terms in Equation I can be assumedto be 1, and Equation I can be then rearranged by straightforwardalgebra to the following Equation K.

Equation K As discussed above the reference to C a carry in an additionof several numbers may be as large as one less than the total of thenumbers being added. Since it is intended to obtain a general expressionfor u which represents the maximum value of u and since each v term canbe one or zero, a general expression for the maximum value of C is thefollowing Equation L.

By replacing C in Equation K with the value defined by Equation L, thefollowing Equation M is obtained.

Equation: M

value is not possible under the circumstances of a quotient defined innatural binary notation. In consequence, the

quantity inside the brackets, since it is preceded by the reciprocal ofthe divisor, invariably must be divisible by the divisor.

1 1 With even divisibility by v 2 +v 2 +v 2 +v established and with uknown (by Equation M) to be no greater than v 2 v 2 v 2 v +1,itisestablished that Equation I permits of solution dictated only by the dvalues of d and greater than the g values of g andgreater, assumingC(X+s+1) is known. This is true because u is at least one less inabsolute maximum value than the divisor which is the only term in thedenominator in the right hand side of Equation I, and also because theright hand side of Equation I must be zero or one. Had the u term, theterm which includes every value assumed to be unknown, been possiblygreater than or equal to V, then solution of Equation I would have beenindeterminate since at least two it values could be found which mightsatisfy the division by 1/ V as described by the right hand side ofEquation I. This is a more generalized statement of the same conclusionobtained in the specific case of the proof of a division by 5.

The following three Karnaugh Maps, one for division by 3, one fordivision by 7, and one for division by 9, were compiled on the basis ofthe above derivation.'The contents of all the boxes in all the maps wereobtained (ac-t2) n l M 6 (xi-Z) 13 BINARY TO DECIMAL CONVERSION Apreferred utilization of this invention is a binary conversion systemwhich I have invented. As is known, a division by ten of a naturalbinary number casts below the binary point a value representative of thelowest ordinal of the number in the decimal notation. Thus, division ofa natural binary number by ten, observation of the remainder, and thendivision once again of the whole number quotient remaining is anattractive means of radix conversion, should the practical problem ofdivision be solved. Since this invention provides a practical, economic,and high speed divider, radix conversion is immediately available.

In a preferred natural binary to decimal radix conversion scheme, twoshift registers are employed in the manner of FIG. 3. The division is byrather than directly by since the result can be interpreted as adivision by ten as described below.

As shown in FIG. 3 a main memory and two shift registers arecontemplated for use in this preferred radix conversion system. Thepreferred system includes a dividend memory 10, dividend shift register12; and memory to shift register transfer circuits 14. Memory 10 is.accessed under the control of a counter and clock 16 in a mannerentirely conventional in the data processing art. Logic is provided soas to produce a unique signal when the count shows the ordinal of anumber accessed in the memory 10 to be an ordinal greater in value thanthe one ordinal. This output is connected through conductive lead 18 toAND circuit 20. In the same manner a signal indicative of the ordinalvalue being equal to or less than one is connected through conductivelead 22 to OR circuit 24.

Shift register 26 is provided for the high order quotient bits. Thequotient bit q is generated in Quotient Logic 28 which is as describedin detail above in accordance with this invention for the division byfive. An output signal of one polarity is produced-0n line 30 as theoutput of quotient logic 28 when q is 1. When q is zero, a signal ofopposite polarity is produced. Line 30 branches into line 32, which isan input of the usual kind to shift register 26. The subsequent divisionof the whole number quotient of a division by 10 is necessary tocontinuethe radix conversion based on the repetitive division by ten' algorismabove discussed. Therefore, line 34 is connected to convey each quotientbit through memory access circuit 16 to dividend memory 10.

Thus, in this preferred embodiment two shift registers:

are employed. The shift register 12 stores the bits d d d and d( ,3) ofthe dividend while the shift register 26 stores the bits q q and q Theoutputs of both shift registers 12 and 26 are pulsed into quotient logic28, and quotient logic 28 then produces an output on line 30 indicativeof the one orzero status of tu At the start of one q determinationcycle, the next lower dividend bit, d isread memory 10 stored in a onebit register 38.

A q determination cycle may be considered to begin with the reading of dfrom memory 10 into register 38 and the simultaneous pulsing of quotientlogic 28 with the output from shift registers 12 and 26. In only a fewmicroseconds, quotient logic 28 will besettled. A conventional source oftiming and clock pulses 40.is provided to automatically initiate a shiftpulse on line 36 and to open memory access circuit 16 to thereby read qinto the dividend memory stage which formerly held.

d The shift pulse also causes the reading of d from store 38 into thefirst stageof shift register 12. The

higher order d bits are advanced one stage and the former d(x+3) bit isautomatically destroyed. The shift pulse on line 36 also causes the (1generated to be read from line 32 into the first stage of shift register26. The higher order q bits are advanced one stage and the former datain the q(x+3) stage is automatically destroyed.

Completion of the shifts initiated by one shift pulse from dividend canbe considered to terminate one q determination cycle. The counter inmemory access circuit 16 is advanced one step during the completion ofthe shifts. A new q determination cycle follows immediately. The memoryaccess circuit 16 then reads the bit of the next lower ordinal of thedividend into the d store 38 as a part of the next q determinationcycle.

The reading of each q into the stage of dividend memory 10 which held dfor that cycle effectively shifts the q down one ordinal. This is aparticular im provement and efliciency of this preferred radixconversion scheme. As is known, a one ordinal shift right accomplishes adivision by 2. Since q is already representative of a division by 5, thequantity inserted in dividend memory 10 is representative of one tenthof the priordividend. The whole number quotient of one tenth of theprior dividend is needed since it is to be divided again in order tocontinue the radix conversion as above discussed.

RADIX CONVERSION-DECODING The division as illustrated in FIG. 3 iscontinued beyond the binary point, since it is the remainder whichdescribes the result of a conversion to one ordinal in the whole numberordinal (the 1 ordinal) of the dividend. is not operated upon during thedivision. That value is stored in d store 38. At the 1 valued ordinaltime.

and at the lower ordinal times the counter of circuit 16 automaticallyceases producing an 0rd 1 signal on line 18. AND 20 will not thenproduce an output since line 18 does not carry one of thetwo inputsrequired by AND 20. Simultaneously, the counter of circuit 16automatically produces an 0rd 1 signal on line 22, and zeroes arethereafter automatically read into shift register 12. The signal on line41 prevents store 38 from being cleared during the three q determinationcycles which follow.

The significance of the 0rd =1 ordinal is stored in circuit 38, but azero is automatically inserted as the significance of the 0rd :1ordinal. It will be proved here that these manipulations do, in fact,preserve an unambiguous modification of the quotient below the binarypoint in a division by ten, and that the whole number quotient obtainedis the same as that of a pure division by 10. This is based upon thefollowing equality, which results inherently from the limitations ofdivision.

Equation 0 VT GQXVE) (W) where, D=dividend V=divisor Also, of course, R=whole number remainder from D divided by V.

remainder and Q willalwaysrepresent the whole num-.

ber portion of a quotient. A subscript to any result, such as Q or Rwill indicate what operation produced the 15 result. Thus, Q indicatesthe whole number quotient from dividing D by 5; and R indicates thewhole number remainder from dividing D by 2. These values may be furtherdivided. Thus,

indicates that the whole number quotient from dividing D by 5 is dividedby 2.

The following Equation P is known directly from the definitions ofdivision and of the terms used:

Equation P T 3=QDno+ f In the preferred radix conversion system inaccordance with this invention, the lowest ordinal of D described innatural binary notation is made zero, even though it may originally beone or zero. Since it is well known that a one ordinal shift right of anatural binary number accomplishes a division by two, the lowest ordinalcan be immediately recognized as describing the Whole number remainderof dividing D by two. In fact, therefore, it is DR which is firstdivided by 5 in accordance with this preferred embodiment. Both thewhole number quotient and fraction parts of the quotient are obtained.This is described mathematically as follows:

In the structural implementation, after the Equation 1 is carried out, asubsequent division by two is accomplished as the quotient bits whichare generated are read into dividend memory in bit positions shifted oneordinal toward the lower ordinals.

Stated mathematically, this is equivalent to multiplying both sides ofEquation 1 by /2. Thus,

[ auer [i] This equation may be simplified by straightforward algebra,it being recognized that division of Q DRn/z [-*5 by two may create anew whole number remainder. Thus, simplifying (2) above,

In accordance with the notation discussed above is the whole numberremainder divided by obtained from dividing by 2 the whole numberquotient produced by dividing Dr- Rp g by 5,

Equation 3 may be further simplified into the following Equation 4,completely by straightforward algebra:

It is now recognized that Equation 4 will be shown to be identical inform to Equation P if the fractional portion,

cannot be greater than 1. Should that fraction portion possibly begreater than one in any case, however, the

term would then not represent the true whole number quotient termobtained in every case. If it can be shown that the value Equations 5and 6 are established by the following, which proves that RD/fl] D-Rm 2cannot be ten in value or greater.

First, it is recognized that the maximum theoretically possible value ofthe above sum of whole number remainders is 10. This is true becauseboth 5 2 and R were produced from divisions by 2. The maximum wholenumber remainer from division by 2, is of course 1. Also,

R [D-Rn/z] 5 is the whole number remainder produced from a division by5. The maximum whole number remainder from division by S is, of course,4. Thus the theoretically maximum value of is shown by inserting theabove terms, to be 1 7 The true maximum value can be shown to be lessthan this, however.

Assume that is the maximum value possible for that remainder, whichmaximum value is 1. If this is true, then 10 was an odd number, sinceonly odd numbers produce a remainder when divided by two.

is the whole number quotient from dividing DR by 5. D-R must be an evennumber since R will be one and will be subtracted away should D be anodd number. Since D-Rn D-R [5 [5] was obtained by dividing D-R by 5. Itcan be immediately stated that F -Run] along with Q =D-RD/2 5Q[D RD]Since [D-Rn/2] was established above as being an odd number, then is oddbecause an odd number multiplied by an odd num ber is invariably an oddnumber.

The equation,

R D RD/z 5Q D on D- u/r [*5 can therefore be written R =Even Number-OddNumber An even number less an odd number is invariably an odd number.Thus, when is 4, an even number, it is established that the three wholenumber remainders:

R can never simultaneously be their maximum theoretical value. Sincetheir maximum theoretical value is ten or less it is established thatthe fractional value in Equation 4 is less than one. Thus, Equation Pand Equation 4 identical in form, and Equations 5 and 6 are proved.

Equation 5 establishes that the number inserted in dividend memory 10 isidentical to the whole number quotient obtained in a standard divisionof D by 10. This establishes that the radix conversion as described andas fundamentally based upon repetitive division by ten of the wholenumber quotient of D/ 10 can be properly carried out with the structuresprovided. Equation 6 is a proof that the whole number value below thebinary point (R in a division of D by 10 is entirely described by thevalues appearing below the binary point in a division of D by 5 in whichthe significance of the ordinal one above the binary point is transposedto zero for the division, but in which independent knowledge of thesignificance of the ordinal immediately above the binary point ispreserved. In other words, it is only necessary to know the significanceof the lowest whole number ordinal of D and the significances of theordinals of the quotient below the binary point.

With the above proof completed, it becomes of importance to determinethe number of quotient ordinals which must be known to describe theremainder unambiguously in a radix conversion. Remainders in a divisionby ten of a natural binary whole number must be integrals of 0 through9. Division does not change the relative magnitudes of values in theoriginal number, but merely reduces all magnitudes by the value of thedivisor. Therefore, a binary one significance of the 1 valued ordinal ofa natural binary number divided by ten will have a contribution in thefinal quotient of one-tenth. A binary one in the next higher ordinalwill have a contribution in the final resulting totalling 2/10, a binaryone in the next higher ordinal will have a significance in the finalresult totalling 4/ 10, and a binary one in the next higher ordinal willhave a significance in the final result totalling 8/10. It isimmediately apparent that only the binary one ordinal contributes avalue of one to the total possible values of 0-9.

Since a binary code decimal (BCD) digit is desired to be decoded out ofthe system in accordance with this preferred embodiment, the value ofpreserving the digit in the binary one ordinal becomes apparent. Thisdigit can be directly observed as the one ordinal output in the BCDoutput decode. As will be fully clarified below, the preservation of thesignificance of the 1 valued ordinal is so used.

As is well understood, the remainder in a binary division appears as adiminishing series in which each ordinal has a value which is a sequenceof negative, whole number powers of two and in which each ordinal mayhave a significance of one or zero. (For example:

Significance is typical). Since a whole number will be divided by ten,the whole number R must be either 1, 2, 3, 4, 5, 6, 7, 8, 9, 0. Thelower valued ordinals are not required, however, to achievedifferentiation between these ten discrete values which are known toexist.

In this radix conversion scheme a whole number which is comparable toD--R in Equation 1 in the above derivation is divided by 5. Since thedividend is a whole number, the high order values below the binary pointmust be representative of one of the possible remainders, which are 0,l, 2, 3, 4. The following table tabulates the four ordinals below thebinary point for the 5 possibilities.

CONVERSION TO WHOLE NUMBER REMAINDER FROM QUO'IIENT BELOW THE BINARYPOINT PRODUCED BY DIVISION BY 5 Quotient Ordinal Value Remainder It willbe noted that the numbers are described uniquely by only the first threeordinals. The last ordinal is therefore shown not to be necessary toresolve any ambiguity.

It is thus established that only the three ordinals of q immediatelybelow the binary point are needed to describe the remainder in adivision of a whole number by five. Equation 6 established that theremainder from a division of D by ten is described by the significanceof the one valued ordinal in Q (which is equal to and by thesignificance of the original 1 valued ordinal of D (which is RTherefore, a methodical compilation was made to include all of the fivepossible combinations of the three highest ordinals immediately belowthe binary point resulting from a division by five as compared with thetwo possible values of the one valued ordinal of the original number (D)and one valued ordinal in a quotient from division by 5 to therebydetermine what the remainder must be in each case. The compilation wasobtained by merely assuming ten different natural binary numbers each ofwhich ended with a different of the ten numbers available in decimal:i.e., XXI, XX2, XX3, XXO. The number was described in natural binarynotation, and the significance of the lowest ordinal was noted. Thenumber with a zero then inserted in the lowest ordinal was then dividedby 5. The resulting significance of the one valued ordinal of thequotient plus the significances of the three ordinals of the quotientbelow the binary point were simply recorded, since these figuresconstituted one result in the following table.

DEOODE TABLE (Division by 5 of DR This decode table was used directly toachieve the decode logic 42 of FIG. 3, which is fully illustrated inFIG. 4. It is apparent from the decode table that the significances ofonly two ordinals below the binary point in the division by 5 arerequired. However, the use of a third ordinal beneficially simplifiesthe decode logic structure as illustrated in FIG. 4.

The decode logic 42 connects with the d store regist6l' 38 and With theIQ/2), q q and guns ordinal registers of memory 10. Since in the actualimplementation of radix conversion as illustrated in FIG. 3 a oneordinal shift is made to achieve a division by 10, g is equivalent tothe l valued ordinal in the above decode table, while 11 q and 11 areequivalent to the /2, A, and /s valued ordinals of the above decodetable. Division is complete for the purposes of radix conversion when aquotient has been obtained which includes the /a valued ordinal in thedivision by 5, and this is shifted one ordinal and is stored as the Avalued ordinal. At this time, therefore, the proper bit stores aredirectly accessed into decode logic 42, as illustrated in FIG. 4. Abinary coded decimal output is obtained immediately and may be used inthe machine in any manner desired. Often it will be used ultimately toactivate a printer to thereby print the number in decimal form.

It should be understood that the decode logic 42 is shown in FIG. 3being driven from memory 10 only for purposes of clarity and as analternative. It is actually preferred for most applications to omit anystages in dividend memory 10 representative of fractional ordinalvalues. Four low order quotient bits would be generated as abovedescribed, but they would not be stored in memory 10. Instead, use ismade of the fact that (1 (1 and QQ/a) are represented by the stages ofshift register 26 at the time qu/m) is generated on line 30 from logic28. Thus, line 30, and the output from the three stages of shiftregister 26, and the output from d store 38 is gated into quotient logic42 at the proper cycle, and the proper output is obtained withoutproviding stages in dividend memory 10 to store fractional quotientbits.

TERMINOLOGY AND NUMBER SYSTEM For a more complete understanding of thefull scope of this invention, discussion will be made concerning theordinal values of a whole number described in any accumulative, carrytransfer scheme of notation. The natural binary numbering system is anaccumulative, carry transfer scheme of notation.

Thus, the ordinal values in a natural binary system are: 1, 2,, 4, 8,16, 32, 2. When a number is described in natural binary notation, someof the ordinal values carry zero significance while the other ordinalvalues carry a one. This is well known. Only the ordinal values whichcarry a one contribute to the final number.

For example, the number 154 is described as: Quotient OrdinalValue OY iirgl vgfifit ordinalvalue 1 i 2 l 4 8 32 64 i ofD resented y; 1 NumberDescriptors 0 1 0 1 t 1 0 0 1 0 0 0 0 0 The number total is a simpleaddition of the ordinal 0 0 0 0 1 1 values of the number descriptorshaving one significance, 1 1 r 65 in this case: -I' "r "3" 0 *f 3128+16+8+2 154 i 1 0 f It will be noted further that each numberdescriptor 0 1 1 0 has an independent significance related directly tothe n ordinal value in Which it appears. Thus, in natural binary 1 0 0 06 notation, when a one number descriptor appears in the 1 O 0 1 1 7 128ordinal, the final number is established as being at 0 1 0 least 128 invalue. The presence of a one number descripn tor in some other ordinaldefines numbers to be added 0 0 1 1 1 9 to the value 128. The presenceof a zero number descriptor indicates that no addition is to be made.The

bare existence of the one in the 128 ordinal is thus seen to define asubtotal which is a part of the final number, regardless of the othernumber descriptors; this characteristic may be thought of as theaccumulative characteristic of the numbering system.

A second characteristic is the carry transfer characteristic of thenumbering system. This characteristic requires that all subordinateordinals represent an amount which differs by one from the next dominateordinal. Thus, in the natural binary system, the subordinate ordinal-s1, 2, and 4 total one less than the next dominate ordinal, 8.Physically, this means in counting that the low ordinals are filled andthat the dominant ordinal is filled from a carry from the subordinateordinals.

The accumulative, carry transfer progression of number values is, infact, the classical and often useful method of number notation. Thedecimal system responds to the same limitations. Thus, the number 58,024is written as follows in decimal notation:

OrdinalValue 1 100 1,000 10,000

Numb er D escript ors 4 2 8 5 In this case the first number descriptor,4, establishes that the final number contains four parts of the ordinalvalue, which is 1. This is true regardless of the other numberdescriptors. Similarly, in the above example, the 8 establishes that atleast eight l,0*00=s exist in the number, regardless of the other numberdescriptors. Furthermore, the decimal system has the carry transfercharacteristic. Thus, 999 is written in the first three ordinals while999+1 is written as 1,000.

In any accumulative, carry transfer system of notation, a column shiftrepresents a multiplication by the radix of the number, and furthermoreall carries have one significance to the next higher ordinal. Thus,since any dividend can be expressed as multiples of the quotient in themanner of Equation E, this invention is applicable for machine divisionof any number stored in the accumulative, carry transfer system ofnotation.

While the invention has been particularly shown and described withreference to preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade therein without departing from the spirit and scope of theinvention.

I claim:

1. A divider for a dividend represented by the conditions of a machinein an accumulative, carry transfer scheme of notation comprising:

means to observe the significance represented by the conditions of amachine of at least one quotient ordinal higher than a lower, quotientordinal being generated,

means to observe the significance of at least one ordinal of saiddividend, and

means responsive to both said means to observe to generate a conditionrepresentative of the significance of said lower ordinal of saidquotient.

2. The combination as in claim 1 also comprising means to store saidlower ordinal quotient significance and to repeat said observations andsaid generation for successive lower ordinals of said quotient and saiddividend.

3. A divider as in claim 1 wherein said dividend is represented in amachine in natural binary notation.

4. A divider as in claim 3 also comprising means to store said lowerordinal quotient significance and to repeat said observations and saidgeneration for successive lower ordinals of said quotient and saiddividend.

5. A divider as in claim 3 wherein said dividend is divided by five,

and said means to observe at least one quotient ordinal 22 observes thesignificance of the three quotient ordinals immediately higher than aquotient ordinal being generated,

and said means to observe at least one ordinal of said dividend observesthe one dividend ordinal which is the same ordinal value as a quotientordinal being generated and also observes the significance of the threedividend ordinals immediately higher than said one dividend ordinal,

and said means responsive to generate a lower ordinal of the quotientgenerates the significance of the one quotient ordinal which isimmediately lower in ordinal value than the lowest valued quotientordinal observed.

6. A divider as in claim 5 also comprising means to store thesignificance of the said quotient ordinal generated and to repeat saidobservations and said generation for successive lower ordinals of saidquotient and said dividend.

7. A divider as in claim 3 wherein said dividend is divided by three,

and said means to observe at least one quotient ordinal observes thesignificance of the two quotient ordinals immediately higher than aquotient ordinal being generated,

and said means to observe at least one ordinal of said dividend observesthe one dividend ordinal which is the same ordinal value as a quotientordinal being generated and also observes the significance of the twodividend ordinals immediately higher than said one dividend ordinal,

and said means responsive to generate a lower ordinal of the quotientgenerates the significance of the one quotient ordinal which isimmediately lower in ordinal value than the lowest valued quotientordinal observed.

8. A divider as in claim 7 also comprising means to store thesignificance of the said quotient ordinal generated and to repeat saidobservations and said generation for successive lower ordinals of saidquotient and said dividend.

9. A divider as in claim 3 wherein said dividend is divided by seven,

and said means to observe at least one quotient ordinal observes thesignificance of the three quotient ordinals immediately higher than aquotient ordinal being generated,

and said means to observe at least one ordinal of said dividend observesthe one dividend ordinal which is the same ordinal value as a quotientordinal being generated and also observes the significance of the threedividend ordinals immediately higher than said one dividend ordinal,

and said means responsive to generate a lower ordinal of the quotientgenerates the significance of the one quotient ordinal which isimmediately lower in or dinal value than the lowest valued quotientordinal observed.

10. A divider as in claim 9 also comprising means to store thesignificance of the said quotient ordinal generated and to repeat saidobservations and said generation for successive lower ordinals of saidquotient and said dividend.

11. A divider as in claim 3 wherein said dividend is divided by nine,

and said means to observe at least one quotient ordinal observes thesignificance of the four quotient ordinals immediately higher than aquotient ordinal being generated,

and said means to observe at least one ordinal of said dividend observesthe one dividend ordinal which is the same ordinal value as a quotientordinal being generated and also observes the significance of the fourdividend ordinals immediately higher than said one dividend ordinal,

and said means responsive to generate a lower ordinal of the quotientgenerates the significance of the one quotient ordinal which isimmediately lower in ordinal value than the lowest valued quotientordinal observed.

12. A divider as in claim 11 also comprising means to store thesignificance of the said quotient ordinal generated and to repeat saidobservations and said generation for successive lower ordinals of saidquotient and said dividend.

13. A divider as in claim 2 in combination with other means adapted, incombination with said divider, to convert a number represented in amachine in one radix to another radix by successive divisions by thevalue of said other radix, at least one of said divisions beingaccomplished by said divider.

14. A divider as in claim 4 in combination with other means adapted, incombination with said divider, to convert a number represented in amachine in natural binary notation to another radix by successivedivisions by the value of said other radix, at least one of saiddivisions being accomplished by said divider.

15. A divider as in claim 6 in combination with other means adapted, incombination with said divider, to convert a number represented in amachine in natural binary notation to a decimal notation by successivedivisions by ten, at least one of said divisions being accomplished bysaid divider.

References Cited UNITED STATES PATENTS 3,223,831 12/1965 Hollerman a-235-164 MALCOLM A. MORRISON, Primary Examiner.

V. SIBER, Assistant Examiner.

1. A DIVIDER FOR A DIVIDEND REPRESENTED BY THE CONDITIONS OF A MACHINEIN AN ACCUMULATIVE, CARRY TRANSFER SCHEME OF NOTATION COMPRISING: MEANSTO OBSERVE THE SIGNIFICANCE REPRESENTED BY THE CONDITIONS OF A MACHINEOF AT LEAST ONE QUOTIENT ORDINAL HIGHER THAN A LOWER, QUOTIENT ORIDNALBEING GENERATED, MEANS TO OBSERVE THE SIGNIFICANCE OF AT LEAST ONEORDINAL OF SAID DIVIDEND, AND